1. Field of the Invention
The present invention relates to a semiconductor device with a vertical transistor, and, specifically, relates to a structure of an upper diffusion layer of the vertical transistor.
2. Description of the Related Art
A vertical transistor with a three-dimensional structure was suggested as a transistor for a semiconductor device in an attempt to reduce the size of the chip and to improve the performance. In such a vertical transistor, a gate electrode is provided through a gate insulating film on the side of a pillar-shaped (columnar) semiconductor (hereinafter referred to as “a semiconductor pillar”), which is to be a channel body portion. Furthermore, diffusion layers (upper and lower diffusion layers), which are to be a source and a drain, are formed on the top and bottom of the semiconductor pillar.
A method of forming this vertical transistor is known, in which semiconductor pillars, which are to be a channel body portion, are formed with a semiconductor substrate engraved; a lower diffusion layer is formed by implanting impurity ions, which are the different conductive type from the channel body portion; and a upper diffusion layer is formed on the top of the semiconductor pillar. In this case, a semiconductor layer including the upper diffusion layer was suggested to be made by replacing a mask silicon nitride film, which has been formed for processing the semiconductor pillar, with single crystal silicon by the selective epitaxial growth method (JP-A 2008-288391).
However, the area of the upper diffusion layer in the direction of a substrate plane is usually the same as the area of the top surface of the semiconductor pillar in the direction of the substrate plane. In case that a gate electrode is formed to extend over a mask silicon nitride film, the area of the upper diffusion layer in the direction of the substrate plane is less than the top surface of the semiconductor pillar in the direction of the substrate plane because the upper diffusion layer is formed after an insulating film side wall is formed for insulation. Therefore, when a contact is made with the upper diffusion layer, the misalignment in the pattern between the contact and the upper diffusion layer causes a problem of short circuit with the gate electrode due to the failure of being formed correctly landing on the upper diffusion layer.
In order to resolve the misalignment of the contact, it is generally known to form a contact pad having a larger plane than the bottom surface of the contact. For example, JP-A 2004-319808 discloses that a deposit conductive film, which has a larger area than that of the top surface of the upper diffusion layer, is formed on the upper diffusion layer of a vertical transistor, or that a deposit conductive film connects the upper diffusion layers of two adjacent vertical transistors and the contact is connected to this deposit conductive film.
While the application of a vertical transistor is more focused on the reduction in the chip size, the contact area between the upper diffusion layer of the vertical transistor and the contact pad tends to decrease. Therefore, the reduced size becomes incompatible with the performance of the vertical transistor due to the increased interfacial resistance between the upper diffusion layer and the contact pad.